Divided into 5 types of work
A normal mode WGM1=0 is similar to the normal mode of 51, there is a TOV1 overflow interrupt flag, which occurs when MAX (0xFFFF)
1 Use internal count clock for ICP capture input occasions-measuring pulse width / infrared decoding (capture input function can work in multiple modes, not just the normal mode)
2 Use external counting pulse input for counting, frequency measurement and other applications, it is more convenient to adopt other modes, and there is no need to worry like 51
Two CTC mode [Clear timer mode when compare match] WGM1=4, 12 is similar to 51 auto-reload mode
1 Used to output a square wave signal with 50% duty cycle
2 It is used to generate accurate continuous timing signal when WGM1=4, the maximum value is set by OCR1A, OCF1A compare match interrupt flag is generated in TOP When WGM1=12, the maximum value is set by ICF1, and ICF1 input capture interrupt flag is generated when TOP
If TOP=MAX, TOV1 overflow interrupt flag will also be generated during TOP
Note: When WGM=15, square wave output from OC1A can also be realized, and it has double buffering function.
Calculation formula: fOCn=fclk_IO/(2*N*(1+TOP)) The variable N represents the prescaler factor (1, 8, 64, 256, 1024), and T2 is two more levels (32, 128).
3 Fast PWM mode WGM1=5, 6, 7, 14, 15 single ramp counting, used to output high frequency PWM signal (double the frequency of double ramp) all have TOV1 overflow interrupt, which occurs in TOP [ It is not MAX. It is different from normal mode and CTC mode] After a comparison match, an OCF1x comparison match interrupt can be generated.
When WGM1=5, the maximum value is 0x00FF, 8-bit resolution
When WGM1=6, the maximum value is 0x01FF, 9-bit resolution
When WGM1=7, the maximum value is 0x03FF, 10-bit resolution
When WGM1=14, the maximum value is set by ICF1, and ICF1 input capture interrupt (single buffer) is generated at TOP
When WGM1=15, the maximum value is set by OCR1A. OCF1A compare match interrupt is generated during TOP (double buffering, but OC1A will not have PWM capability and can only output a square wave at most). When changing the TOP value, it is necessary to ensure that the new TOP value is not less than all Compare register value
Note that even if OCR1A/B is set to 0x0000, it will output a narrow pulse of the timer clock cycle instead of always being low.
Calculation formula: fPWM=fclk_IO/(N*(1＋TOP))
4 Phase correction PWM mode WGM1 = 1, 2, 3, 10, 11 double ramp counting, used to output high-precision, phase-accurate, symmetrical PWM signals have TOV1 overflow interrupt, but it occurs after the comparison match in BOOTOM OCF1x compare match interrupt can be generated.
When WGM1=1, the maximum value is 0x00FF, 8-bit resolution
When WGM1=2, the maximum value is 0x01FF, 9-bit resolution
When WGM1=3, the maximum value is 0x03FF, 10-bit resolution
When WGM1=10, the maximum value is set by ICF1, and ICF1 input capture interrupt (single buffer) is generated at TOP
When WGM1 = 11, the maximum value is set by OCR1A. OCF1A compare match interrupt is generated during TOP (double buffering, but OC1A will not have PWM capability and can only output square waves at most). When changing the TOP value, it is necessary to ensure that the new TOP value is not less than all The value of the comparison register can output a PWM signal with a duty ratio of 0% to 100%. To change the TOP value during T/C operation, it is best to use the phase and frequency correction mode instead of the phase correction mode. If TOP remains the same, then there is actually no difference between these two working modes
Calculation formula: fPWM=fclk_IO/(2*N*TOP)
5 Phase and frequency correction PWM mode WGM1 = 8, 9 double ramp counting, used to output high-precision, phase and frequency are accurate PWM waveforms have TOV1 overflow interrupt, but occurs in BOOTOM comparison match can generate OCF1x comparison Match interrupt.
When WGM1=8, the maximum value is set by ICF1, and ICF1 input capture interrupt (single buffer) is generated at TOP
When WGM1=9, the maximum value is set by OCR1A. OCF1A compare match interrupt is generated during TOP (double buffering, but OC1A will not have PWM capability and can only output square wave at most). The main of phase frequency correction PWM mode and phase correction PWM mode The difference is that when the update time of the OCR1x register changes the TOP value, it must be ensured that the new TOP value is not less than the value of all compare registers. It can output a PWM signal with a duty ratio of 0% to 100%. When a fixed TOP value is used, it is better to use the ICR1 register to define TOP. In this way, OCR1A can be used to output PWM waves in OCR1A. However, if the PWM base frequency is constantly changing (by changing the TOP value), the double buffering feature of OCR1A makes it more suitable for this application.
Calculation formula: fPWM=fclk_IO/(2*N*TOP)
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