With the development of Digital Signal ProcESSor (DSP) technology, DSP has been widely used in radar, communications and other fields. Although DSP has experienced several generations of development, the computing speed and capabilities have been greatly improved, but in many cases, single-chip DSP can not meet the requirements of real-time processing, and must seek multiple DSP parallel processing solutions.
From the system structure, the parallel system can be divided into a shared memory parallel system and a distributed memory parallel system. The SHARC series of DSP chips from AD also support these two parallel processor architectures. In general, a series of two-bit high-performance floating-point DSPs from AD Corporation is called SHARC (Super Harvard Architecture). For shared memory systems, this is done via an external shared bus between SHARCs. For the distributed memory system, the link between the two SHARCs is directly connected to realize point-to-point communication between the DSPs.
However, parallel processing cannot be considered as a hardware connection of multiple SHARCs to each other. The true parallel processing should be to enable the interconnected DSPs to coordinate work and shorten the processing time of the system. This requires the transfer of data streams between SHARCs in a parallel system. The transfer of data streams between SHARCs in a parallel system is as important as data processing. In this paper, the software design method and design technique are given for these two parallel methods, and the program implementation for ADSP2116X is given.
1 shared memory parallel system design
SHARC provides powerful support for multi-processor systems, allowing users to form a shared memory parallel system without any additional peripheral circuitry. SHARC has a clever set of distributed bus arbitration mechanisms. The external bus can be shared by connecting two to six SHARCs to connect the corresponding pins of each SHARC. Each SHARC can access the on-chip memory of other SHARCs, and can also initiate other SHARC DMA operations by setting the IOP register.
When forming a shared memory parallel system, each SHARC has a unique identifier: ID2~0, ranging from 000 to 110. ID=001 indicates that the SHARC is DSP No. 1, ID=010 indicates that the SHARC is DSP No. 2, and so on. ID=000 indicates a single DSP system. In a multi-DSP system, the DSP with ID=001 must exist, which is the main processor after the DSP is successfully loaded.
In a shared memory system, only one SHARC can drive the external bus at any time. The SHARC is called the main processor. The remaining slave SHARC must first apply for the bus if it needs to access the bus. If the main processor does not have data transfer or bus occupation time at this time, it will release the bus control right, drive its own external bus to three states, and complete the transfer of bus control rights.
The main processor is as simple as accessing memory from the SHARC and accessing its own memory, either directly through the kernel or by external port DMA. In a shared memory parallel system, each SHARC has a mapped multiprocessor memory space based on its own ID number. For example, for the ADSP2116X, the SHARC corresponding to the SHARC of ID=001 is 0x100000 to 0x1F FFFF, and the SHARC corresponding to the SHA12 corresponds to the multiprocessor memory space of 0x20 0000 to 0x2F FFFF. The LDF file for a shared storage system is somewhat different from a single DSP system. An example of this is given below (take 2 SHARC as an example).
Example 1: Shared memory system LDF file.
ARCHITECTURE(ADSP-21160)
SEARCH_DIR($ADI_DSP211xxlib)
MPMEMORY{
DSP1{START(0X100000)} //The first DSP is in multiple processing
// mapped space of the device space
DSP2{START(0X200000)} } //The second DSP is in multiple processing
// mapped space of the device space
MEMORY
{pm_rsTI { TYPE(PM RAM)START(0x00040004)END
(0x0004000f)WIDTH(48) }
Pm_code { TYPE(PM RAM)START(0x00040100)END
(0x00049fff)WIDTH(48) }
Dm_data { TYPE(DM RAM)START(0x00050000)END
(0x00059fff)WIDTH(32) } }
PROCESSOR DSP1
{LINK_AGAINST(DSP2.DXE) //Reconnected
/ / DSP2 target file
OUTPUT (DSP1.DXE) / / DSP1 output target file
...... // is the same as a single DSP system, so it is omitted, the same below
}
PROCESSOR DSP2
{LINK_AGAINST(DSP1.DXE) //Reconnected
/ / DSP1 target file
OUTPUT (DSP2.DXE) / / DSP2 output target file
......
}
In this way, the two DSPs can access each other's internal resources through the external bus. When DSP1 needs to directly access a variable in DSP2, only DSP2 needs to set the variable to global type. DSP1 can directly access the variable through the external bus in the multiprocessor space. Of course, it can also be based on the memory address of the variable. direct interview.
In a shared memory parallel system, when data is transferred between two SHARCs via the bus, if other DSPs need to access the external bus at this time, only the pending waits. In this way, when data exchange between multiple DSPs is frequent, the efficiency of the system is greatly reduced. In addition, in a shared memory parallel system, only up to six DSPs can be connected to each other. If more DSPs are needed to work in parallel, the shared memory parallel system will be powerless. This problem can be effectively solved by using the distributed memory parallel system described below.
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