Basic problem in AD conversion design

The AD program is to imitate someone else's existing program. On the basis of this modification, the result is debugged for about a week. How can I adjust it and debug it? Finally, at the teacher's point, I found the reason. On the one hand, the debugging method is wrong. On the other hand, the understanding of the datasheet is not enough. There are several aspects:

I. The debugging method is wrong. I wrote the program myself, and then changed my own program to someone else. The writing was very messy. If something went wrong, it would be difficult to find it. It may be multiple errors. It is not easy to check.

2. There is no such thing as debugging. You should learn to analyze. When you write a program, you should first analyze the software error. If the software is not wrong, analyze the hardware error, and I feel confused when debugging. There is no correct order.

Finally, I found out which function has made a mistake, but how can I not adjust it, or the understanding of the datasheet is not enough, that is, when SCL is at a high level, SDA is valid, which is in front and which is in the back. The timing is chaotic, the timing is not right, and the data cannot be read.

Error one:

Right:void slave_NOACK(void)

{

SDA = 1; //

SCL = 1; // This order is exquisite. If SCL is in front, then the SDA before this timing is also valid. If the previous SDA is low, it will cause a jump.

delayNOP();

SDA = 0;

SCL = 0;

}

Wrong:void slave_noack()

{

SCL=1;

SDA=1;

delayNop();

SDA=0;

SCL=0;

}

Error 2: The IIC bus initialization is not added. If it is not added, the IIC may be in working state, and the timing of the AD will be disrupted.

Right: iic_init(); //I2C bus initialization

PCF8591_ADC(0x04);

If(systemerror == 1) //has an error, come back

{

Iic_init(); //I2C bus initialization

PCF8591_ADC(0x04);

}

Void iic_init()

{

SCL=0;

iic_Stop();

}

The following is a summary of the basic problems in the AD conversion design, a total of 82, relatively long, hypnotic effect before going to bed!

1. How to choose the signal conditioning device before high-speed analog-to-digital conversion; how to solve the synchronization problem of multi-channel analog-to-digital conversion?

The most fundamental principle of signal conditioning before the ADC is that the noise and error caused by signal conditioning are within one LSB of the ADC. For this purpose, it may be necessary to select an op amp with the appropriate indicator. As for the problem of multi-channel ADC synchronization, there is usually a chapter in the data sheet of the high-speed ADC to introduce the multi-chip synchronization problem. You can look at the introduction.

2. How to determine the internal noise parameter when selecting an ADC?

Generally, the ADC has a signal-to-noise ratio SNR or a signal-to-analog ratio SINAD. SINAD=6.02* effective digits +1.66. You can use this formula to determine whether the ADC you choose can meet your requirements.

3. How to calibrate the pipeline structure ADC? Which parameters need to be calibrated?

In general, the ADC's offset and gain errors are easier to calibrate. As long as the external 0V and full scale are sampled, then the calibration coefficient is obtained. In addition, if temperature compensation is required, it is generally necessary to add a temperature sensor and then use the look-up table to compensate.

4. What are the recommendations for cabling around the ADC and DAC?

ADCs and DACs are analog-digital hybrid devices. The most important thing in layout and routing is to pay attention to the problem of analog ground and digital ground processing. For devices with high sample rates, a piece of ground is recommended. For devices with low sampling rates, it is recommended to separate the analog digitally and finally connect them together below the chip.

Other place and route specifications are the same as for other devices.

For a specific device, there is usually a layout drawing of the evaluation board for reference.

5. Is there any necessary connection between the accuracy of the analog-to-digital converter and the noise figure?

The accuracy of the low-speed analog-to-digital converter is expressed in terms of peak-to-peak resolution and rms resolution. The rms resolution metrics for different cases are listed in the chip data of some Sigma-delta ADCs in ADI. The accuracy of high-speed analog-to-digital converters can be expressed in terms of SNR, SNOB, and these metrics can also be found in the data.

However, there is no noise figure (NF) indicator in the general ADC index.

6. If an external analog switch is used, then there is always some resistance in this switch, which will inevitably cause some errors. Then I would like to ask if there is any way to reduce these errors, and describe the hardware method and software. method.

You can choose a switch with a small resistance such as the ADG14** series. If the switch is for channel switching, add an op amp to follow in the latter stage. If you are doing range switching, you can only select switches with small resistance, and pay attention to the flatness and temperature drift parameters of the switch. If the system requires high precision, you can only do software calibration or select a programmable amplifier such as AD8250/1/ 3 and so on.

7. After the input end of the AD7710 is short-circuited with its own ground, when the data is read, the AD conversion value jumps relatively loudly. By explaining several calibration methods, the frequency is already solved at 25 Hz. I do not know how to solve?

Please confirm the stability of the power supply and the reference. Under the condition of the frequency of 25Hz and the gain of 1, look at the data in the hand test. Table II shows that the effective value resolution is 21.5bit, then the actual peak-to-peak resolution is 21.5-2.7. =18.8bit, which means that if there is a 5-bit code, it is normal.

8. Is the input of the ADC connected to the sensor, how to eliminate the interference of the sensor output signal itself?

If the sensor output is common mode interference, you need to add instrumentation op amps such as AD8221/0 to filter out. If it is differential mode interference, the filter can be filtered out.

9. I want to design a 16-channel data acquisition system. The sampling rate of each channel is 100K, 16BIT. I would like to ask what kind of AD chip I want to use. In addition, the input channel of the AD converter is relatively small. External multi-channel analog switch? In addition, what are the requirements for the choice of analog switch, which parameters to pay attention to.

We don't have 16bit and 16 channel ADCs, you can choose to use two AD7689, 16bit 8 channels. Or choose 16:1 ADG1206. Pay attention to on-resistance, charge injection, on-time, etc.

10. A 12-bit high-speed analog-to-digital converter can not be reduced and reduced to 8 bits for use, because our system accuracy only needs 8 bits, which is harmful.

When you read the data, you only need to read 8bit.

11. There are some ADCs with anti-aliasing filters integrated. What are the benefits?

The general anti-aliasing filter refers to the filter at the front end of the ADC, and the sigma-delta ADC integrates some traps inside to realize the power frequency 50Hz and 60Hz notch. The overall benefit is that the ADC has better anti-noise performance. .

12. How can I reduce the interference between adjacent channels?

In the layout and routing, you can consider adding ground shielding between adjacent channels.

13. Want to design high-precision calibration instruments, such as DC voltage output (millivolts), can you recommend several chips? How to eliminate the accompanying quantization noise? How to ensure the accuracy of the ADC, the full-scale of AD conversion is the power supply voltage, For single-supply operation, the zero point determination and range are related to the power supply voltage. If the power supply voltage fluctuation is bound to cause conversion error, how to solve it in the circuit, especially for small signal acquisition. What is the output static error of the DAC? How to increase the number How well does the resistor or current source unit match in the analog converter? Is there a need to connect small inductors between the digital ground and the analog ground when powering the ADC?

1) ADI's op amps, instrumentation products are many types, it is best to list detailed indicator requirements, so it is easier to find.

2) The quantization noise of the ADC is inherent and cannot be eliminated.

3) The power supply of the ADC has a direct impact on the measurement accuracy. Therefore, it is necessary to select a high-precision, low-noise power signal, and also pay attention to avoid interference when wiring.

4) In the general manual, zero error, gain error, etc. will be given separately. I don't know which one is specifically asked, or I can give an example of a specific model.

5) This should be a problem with the internal structure of the DAC. Generally speaking, we don't care about the absolute value of the internal resistor or current source, and only care about the ratio between them. The current process can guarantee this well.

6) Generally speaking, it is enough to connect with a 0 ohm resistor.

14. The larger the internal gain of the ADC, the greater the noise it produces. Can the expert explain the principle between the two?

The larger the PGA gain inside the ADC, the more the noise of the PGA itself will increase, and the more the ADC input noise is amplified. Therefore, the larger the internal gain of the ADC, the smaller the resolution.

15. What is the effect of power supply ripple on conversion accuracy?

If the ADC has a PSRR indicator, this indicator can be used to calculate the effect of power ripple on the ADC. If not, the general reference source has this indicator, you can use the PSRR of the reference source to calculate the impact on the ADC sampling.

16. How is the data converter designed for wiring length, communication crosstalk, and matching resistance?

High speed ADCs will consider these issues. Especially for the ADC of the LVDS interface, try to ensure that the wiring of a pair of signals is equidistant and equidistant, and place the terminating resistor. This aspect of layout is best done with reference to the evaluation board.

17. What is the maximum speed of high-speed digital-to-analog conversion of ADI products? Is the stability of the high-speed sampling frequency reduced?

Our DACs have a maximum speed of 2.5 GHz, which is the AD9739 current output type, which does not affect stability.

18. The nominal number of bits in the ADC is very high, but the actual number of bits at the end is overwhelmed by internal noise. How do I determine the internal noise parameter when choosing an ADC?

For high-precision ADCs, a parameter with an effective resolution is generally given, that is, the number of bits that the device can achieve without skipping. In addition, the power supply, the noise of the reference voltage, and the noise introduced by the ADC front-end conditioning circuit are also considered in the design. These noises need to be controlled within one LSB of the ADC.

19. When evaluating ADCs, it is difficult to evaluate SNR. Therefore, I generally consider evaluating the frequency of hopping at grounding to compare the differences between two similar ADCs. Is this evaluation method scientific? Is there a more scientific method? Is there a specific document?

In fact, for high-speed ADCs, it is necessary to add a high-precision reference signal, and then use ADC sampling, and then perform FFT analysis to evaluate SNR. For high-precision ADCs, this is the method you can use. Please refer to our application note AN-835.

20. How to understand the slew rate indicator? Why limit the voltage change rate?

As a simple example, if the slew rate is not enough, then the actual output can't keep up with the change of the input signal, so the processing of the signal will be distorted.

21. How much influence does the switching power supply ripple have on the 12-bit ADC? Is it necessary to separately handle the power supply ripple for the ADC part?

High-precision ADCs, such as 16-bit and above ADCs, are not recommended for switching power supplies.

22. Does replacing a traditional LDO regulator power supply with a high-efficiency switching regulator have a negative impact on the high-speed analog-to-digital converter? What is the impact on product life?

In high-speed ADC applications, there is a high requirement for ripple and noise of the power supply. Switching power supplies are more efficient, but have larger ripple and noise, which can affect the accuracy of the system. In high-speed applications, SNR and SFDR requirements are relatively high, so it is better to choose LDO.

23. How do you pay attention to the impedance matching of an op amp?

Impedance matching needs to be considered only at high speeds.

24. Will the accuracy of the power supply cause the accuracy of the ADC not to be improved?

possible. The specifics depend on the number of bits in your ADC and the PSRR parameter. If the number of bits is very low, such as 10bit, you can only use 10bit accuracy with a low noise power supply. But for a 16-bit system, if you use a very noisy power supply, the system accuracy will not reach 16 bits.

25. What kind of performance indicators should the AD anti-RF interference filter generally achieve, such as the cut-off frequency and roll-off?

Depending on your application, it is ideally the cutoff frequency is equal to the effective input signal, and the roll-off characteristic is infinitely steep, but there is actually no such filter, and the closer to the ideal, the higher the cost, Eclectic consideration.

26. How to suppress input "glitch"?

Add filter suppression, or digitally filter the sampling results.

27. Are there any good suggestions for using software to improve the accuracy and number of bits of the ADC?

Please pay attention to the quality of the reference and power supply, and also pay attention to layout to prevent noise from being introduced.

28. How much resolution do I need for AD conversion of ECG signals? Can I recommend several models?

Depends on the ECG's signal chain. If the signal chain is AC isolated, the signal can be amplified a lot, such as 1000 times magnification, so that the ADC is selected from 12 bits to 16 bits. If the signal chain is DC isolated, the signal can not be amplified a lot, the general gain is 10, so the number of bits of the ADC is chosen to be larger, 18 to 24 bits.

ECG products will have corresponding standards, that is, ECG products can distinguish the small signal, and the selection of ADC is also related to this.

29. The chip used in an FPGA-based DDS system I designed is the AD9777. Can I share the 3.3V digital power supply between the DA chip and the FPGA chip in the system power supply design when the current is sufficient, so as to simplify the power supply design? purpose?

can.

30. With the increasing popularity of digital video signal applications, will digital-to-analog converters be useless in video, or even eliminated?

Digital-to-analog converters will not be eliminated, because in the end it is necessary to transfer digital signals to analog signals that people can recognize.

31. Under harsh environment (at high temperature), how is the power supply of the ADC designed? Generally, DC-DC is difficult to reach +85 degrees Celsius. Does ADI have a related reference design?

Choosing the right device, DC-DC can work at 85 degrees. The key is to choose the right device and the right design, so that the temperature rise of the system is within its calibration range, such as adding a fan or heat sink. Efficiency and so on.

32. When I use the A/D of the ADuC841, the data collected occasionally will be zero. Why? How to solve it?

In this case, use an oscilloscope to monitor the input signal and see if the input really jumps. If not, please check the ADUC841 data reading program carefully.

33. When adding a DC signal to the converter input, how do you determine the number of digits that should appear on the output?

Generally speaking, according to the calculation formula, Vin/Vref=code/2^N. N is the number of bits of the ADC, Vin is the input voltage, and Vref is the reference voltage. If there is a negative voltage, you need to consider the type of output codeword, such as twos complement. A map is given in most of the ADC's data sheets to illustrate this problem.

34. When the AD7710 is used, the noise is too high. How to use the calibration in the manual? How to do it during the wiring process?

It is recommended to refer to the evaluation board of the chip for layout design.

35. How can I minimize the impact of system noise on the ADC?

Minimize input noise (ADC with differential input) to reduce power supply noise. Design a suitable filter, etc.

36. How do you determine the effect of temperature on the baseline and the impact of multiple final conversion accuracy?

The benchmark chip data will have a temperature coefficient index that affects the baseline, typically a few ppm/°C.

The general ADC chip data has no test parameters that affect the performance of the ADC with reference voltage changes with temperature.

37. How to implement THD test for high speed ADC?

In practice, a high-precision reference source is added, and then ADC sampling is performed, and then FFT analysis is performed. For details, please refer to the introduction of AN-835.

38. Is there any way to reduce the noise of the switching power supply on the ADC?

Add LC filtering, and the reasonable layout is digitally separated as analog. If it still doesn't work, only low noise LDOs can be added.

39. If the linearity of the transfer function of the ADC is relatively poor, how to perform calibration, is there a scientific method for verification? Can it be exemplified?

In general, linear correction is performed. If the calibration does not meet the requirements, it is recommended to use the segmentation correction method.

40. Compared to single-ended, differential has many advantages, but there are still many single-ended ADCs. Is there any weakness in differential mode?

The peripheral circuitry is relatively more complex than a single-ended input.

41. How do we determine the sampling rate and memory bandwidth in the design of high-speed data acquisition systems?

The sampling rate is determined by the frequency of the signal to be processed. The memory bandwidth is determined by the sample rate and processor power.

42. What kind of performance indicators should the AD anti-RF interference filter generally achieve?

Depending on your application, ideally, only signals within the effective bandwidth will pass, but the filter design is difficult to achieve the ideal situation, so compromise.

43. If you choose a converter for digital-to-analog/analog conversion of a video signal, what are its key specifications?

Mainly depends on the video signal format you need to convert, you do not need to do color space conversion. Is the ordinary parallel port interface or HDMI interface.

44. What is the main cause of the output delay of the ADC?

This is determined by the internal parameters of the ADC, depending on the data sheet of the different models.

45. How can I reduce the truncation error and gain error?

For a particular ADC, its Offset error and Gain error are essentially constant. However, Offset error and Gain error can be eliminated by software correction.

46. ​​There is always a wrong code in the collected data. Is there any way to eliminate this error code?

First determine if the error code is an ADC output error or an MCU read error. If it is the former, it depends on whether the design of the system is reasonable and whether the layout is reasonable.

47. Does the ground of the switching power supply need to be separated from the analog ground of the ADC?

The analog ground of the ADC is connected to the ground of the switching capacitor power supply output filter capacitor to reduce the influence of the power supply ripple on the ADC.

48. What does the PSRR indicator mean?

Refers to the power supply voltage rejection ratio.

49. Recently I identified a dual power ADC. I grounded the input of the converter under test and observed the digital output on the LED. What surprised me was why the output digital range I observed was not a digital I expected?

There are many reasons for this problem: the range of the input signal source, the value of the reference voltage source, the effects of noise, and so on.

50. Why can't the quantization noise of ADC be eliminated?

Because sampling is not ideal, it is the concept of infinite approximation.

51. Which indicators of INL and DNL are more meaningful to users in practical applications?

Both of these indicators are important.

52. What should be the final connection between analog ground and digital ground?

Try to separate the analog ground from the digital ground in order to avoid mutual interference. But in high-speed ADC applications, digital and analog requirements are common.

53. I now need to install a space-saving data converter and think that a serial converter is suitable. In order to choose and use this converter, what do I need to know?

The serial interface ADC generally has a low conversion speed of less than 10M, but it is convenient to package and read. You can first look at the number of digits you need, and if you are below 10M, you can't meet your requirements. Another key is the interface between the MCU and the ADC, whether it is an analog SPI or a standard SPI interface of the MCU.

54. What are the requirements for the ad clock signal? Do you need to do some temperature and jitter compensation?

No compensation is required. Related compensation has been done internally in the ADC.

55. For a single-board structure, if there are multiple ADCs on the board, such as 9 ADCs, this lecture is to suggest that the ADC bridges the analog ground and the digital ground. Does it mean that multiple points are grounded?

The ADC needs to be connected to the analog part of the system.

56. When to use FPBW, when to use small signal BW, the data sheet does not tell us everything.

FPBW is related to the Slew Rate of the chip. When the signal is to be amplified, if the Slew Rate cannot keep up, the output signal will be distorted. FPBW = SlewRate/2piVp, Vp is the voltage of the output signal.

57. Ask the experts, when using R, C isolation, if R is larger, it will affect the ADC behind. If C is large, it will affect the phase. How to choose the specific design?

You can consider adding a first-level op amp to the buffer after RC filtering.

58. What are the most common errors in data converters? How to avoid them

The ADC conversion is affected by Noise. If the result of the ADC conversion is approximately equal to the theoretical value, then the conversion result can be averaged to obtain a more accurate value by reading the conversion result multiple times on the same input voltage.

59. The bandwidth we want is 100hz. The result is an amplifier with a bandwidth of 1khz. How to effectively solve the anti-interference problem?

In general, the ADC front end needs to add a filter to filter out noise outside the useful bandwidth.

60. What are the important parameters affecting the ADC? How to avoid it in the pcb design?

Consider the design of the anti-aliasing filter at the front end of the ADC, impedance matching, and impedance of the input and output.

61. In high-speed analog-to-digital conversion, is it not possible to use the internal reference voltage of the chip, and an external reference is required. Is it possible that the internal reference voltage of the chip is as stable as the general external reference?

Using the internal reference voltage, since the reference voltage will sink/source current during ADC conversion, this will affect the supply voltage of the ADC, which in turn affects the SNR of the ADC. External references are often used in applications where high system accuracy is required.

62. At present, the resolution of ADI's ADC chip is higher than 14bit, what is the maximum rate? The dual channel, the resolution is higher than 14bit, what is the maximum rate?

The 14-bit ADC is up to 150 MSPS.

63. What is the problem with the transfer function discontinuity (DNL discontinuity)? If I encounter this problem in the application, what should I do? Use software compensation? If it is not continuous, why can't the chip compensate from the hardware point of view?

DNL discontinuity can lead to lost code. There is no way to compensate externally for this problem. This is the characteristic of the ADC itself. ADI's ADCs are guaranteed to have no missing codes.

64. How much influence does the switching power supply have on data conversion errors? How high is the recommended frequency of the switching power supply?

You can add LDO or LC filters to reduce power supply ripple and noise. Generally, the PSRR of an ADC will be relatively high, and an ADC with a low number of bits, such as 10 bits, is not required for power supply, but a high-order ADC such as 16-bit has a relatively high requirement for a switching power supply. Switching power supply frequency selection is related to power and efficiency. The common switching frequency is generally selected from 100KHz to 300KHz.

65. From the point of view of signal-to-noise ratio, is it necessary to implement multi-channel AD by using a single multi-channel AD chip? Or is it better to use multiple single-channel AD?

It would be better to use multiple ADC chips. Because of the single-chip multi-channel chip, there is interference between the channels.

66. How to judge whether the conversion error is caused by the interference signal or by the conversion itself?

For high-frequency, use a high-precision reference source, high-precision can short-circuit the input to test the noise characteristics of the ADC itself.

67. Is it beneficial to use LDOs behind a switching regulator in order to reduce high frequency interference?

There will be benefits. You can choose a low noise LDO.

68. Which type of A/D should pay special attention to the suppression of electromagnetic interference when wiring? Is there any good advice?

Generally speaking, the ADC does not need to consider this, but considers electromagnetic interference suppression at the power supply end. If a high speed digital device or clock is used, consider adding a shield.

69. What is the difference between a notch filter and an anti-aliasing filter?

The trap is to attenuate the interference at a certain frequency, which can be understood as a band-stop filter, and the anti-aliasing filter can be understood as a low-pass filter.

70. Does noise aliasing cause the ADC's SNR to drop?

Aliasing is due to the signal frequency of <2 times the sampling rate, which makes the design of the filter difficult, so that the filtering of noise becomes difficult and the SNR is also affected.

71. What is the impact on EMC performance when the LDO is powered by the ADC instead of using a switching power supply to power the ADC?

This depends on the EMC processing of your switching power supply. If the switching power supply EMC/I is not handled well, the system will have EMI/C problems. Switching from the LDO to the ADC to supply power to the ADC using a switching power supply can affect the accuracy of the ADC.

72. If a very low frequency analog signal (less than 10 Hz) is measured, which method is more accurate than direct single-ended measurement and driving the ADC after converting the signal into a differential signal?

You can measure directly with a single end.

73. Is the pulse mode A/D timing control complicated? Is it implemented internally by A/D?

For the user side, it is not complicated to use the CPU to control the communication interface of the ADC.

74. In order to eliminate noise interference, how can we minimize the AC loop?

When laying out the wiring, try to consider the return path of the signal line as much as possible so that the loop area is as small as possible.

75. Now I want to use a 16-bit high-speed ADC for a project, but the noise of the front-end analog signal itself is relatively large, and the accuracy of 3~4 bits is wasted. Do you think it is necessary to select a 16-bit ADC?

If the noise of the input signal itself is only 12 bits and cannot be processed to reduce the noise, then do not use a 16-bit ADC.

76. There are many analog power pins on the general ADC package. For example, the AD7656 has 8 AVccs. How do you connect them to the power supply when designing the PCB?

It is best to have a power plane, connect the AVCC to the power supply, and pay attention to the distribution of the capacitor. The new design recommends the AD7656-1, which requires less capacitance on the -1 power supply pin than the AD7656.

77. Can experts recommend several high-precision operational amplifiers for low-temperature drifting Rail-to-Rail?

AD8628, AD8638

78. Many of the current systems are powered by a single switching power supply. What about the digital power supply, analog power supply, digital ground, and analog ground for the ADC and DAC in the system?

Digital power can be drawn from the analog power supply through a magnetic bead. If possible, use separate power chips to power both analog and digital power supplies.

79. Some ADCs will add a high frequency jitter source to the clock input. Can this increase the effective number of bits of adc?

It can be powered from a single supply, but be aware that the AD620's Reference needs to be connected to a supply voltage of 0.5.

80. How can I avoid signal loss when sampling?

Only by increasing the sampling rate or filtering.

81. How do you distinguish whether the interference is coming in from the front end or from the power supply?

For high-precision applications, the input can be shorted to measure the output. If the interference remains the same, it should be caused by the power supply and reference.

82. Is there any difference in the processing of interference between high-speed ADCs and low-speed ADCs?

The same is to add a tantalum capacitor to eliminate interference. The layout may be somewhat different. High-speed ADCs typically sample the ground plane and are grounded nearby. The low speed is typically digitally analog grounded and grounded separately.