At present, with the increase of speed and precision, the A/D converter becomes more and more expensive, which brings difficulties to practical applications. However, in some cases, the change of the measured signal is slow, and the conversion speed is not a major problem. At this time, a low-speed dual-integration A/D chip can be used. For example, the ICL7135 (domestic model 5G7135) is 4 and 1/2 digits, and the resolution is 1/40 000. The accuracy is equivalent to a 14-bit binary A/D converter. MC14433 (domestic model 5G14433) is 3 digits with a resolution of 5/10 000. Both 5G7135 and 5G14433 use dual-slope operation, so they have high resistance to power frequency interference. However, the conversion rate is low, 2 to 10 times per second. If the slew rate is required to be 20 times/second or more, there is no ready-made double-integral A/D conversion integrated circuit. In principle, an integrator, a comparator, and a counter can be used to form a high-precision A/D with high speed, but it is difficult to implement due to limitations in device performance, such as the limited gain of the voltage comparator and the limited slew rate. Another effective way to balance price and conversion accuracy is to use V/F technology to form a high-precision A/D converter. In recent years, due to the development of integrated circuit technology, the price of V/F chips has decreased, and the technical indicators have been further improved. In particular, monolithic V/F chips have been widely used in various industries. The AD650 is a high-precision, monolithic V/F converter that combines with a microcontroller to form an A/D converter with high resolution and a slew rate of more than 20 times per second.
1. The basic principle of analog-to-digital conversion between VFC and single chip microcomputerAs shown in Figure 1, before the conversion, the MCU first clears the counter and the timer, presets the count and the initial value of the timing; then passes the timing control terminal and the counting control terminal to make the timer and the counter start working at the same time; after a certain time The timer overflows to send a signal. After the MCU detects the signal, it stops the counter operation and sends the counting result to the memory. This completes an analog to digital conversion. The frequency of the rectangular wave output by the VFC is linear with its input voltage. The counter value is equal to the VFC output frequency multiplied by the timer time, and the timer time can be precisely controlled by the microcontroller. Therefore, the conversion accuracy of this method mainly depends on the accuracy of the VFC.
2. Hardware design of interface between AD650 and single chip microcomputerThe AD650 is a charge-balanced monolithic V/F converter, and Figure 2 is its electrical schematic.
The wiring of the AD650 is not very complicated. It is only necessary to select the values ​​of the four components: input resistor RIN, timing capacitor Cos, logic resistor Ro and integral capacitor CINT. The selection principle is described below.
Ro: According to the TTL logic level, the transistor T has a voltage drop of 0.4 V when it is turned on. To ensure sufficient load capacity, it is desirable to have a current of 8 mA flowing through Ro. This is R. It is approximately 0.5 V / 8 mA = 62.5 Ω, generally 1 kΩ. If 1MHz is selected as the full-scale frequency, a pull-up resistor of about 500 Q must be used to obtain a sufficiently short rise time.
RIN and COs: These two parameters determine the full scale frequency and the appropriate input signal voltage range. The relationship between RIN and Cos is non-linear. When the full-scale frequency is 1 MHz and the input signal is 0 to 10 V, Cos can be 51 pF and RIN is 16.2 kΩ.
CINT: In most cases, the best value for CINT is calculated as follows:
At 1 MHz, CINT should still take 1000 pF.
The timers and counters used for analog-to-digital conversion are implemented using the 8253 chip produced by Intel Corporation. It has three independent 16-bit down counters with preset numbers. Each counter has a clock input CN, a gate input GN, and an output ON. The clock input is used to input a clock pulse or an event count pulse. The value of the counter changes on the falling edge of the clock pulse, and the gate terminal can send a control or reset signal. When the counter is reduced to zero, the flag signal is sent from the output.
Figure 3 is the wiring diagram. The output of the AD650 is connected to the CN terminal of the 8253 counter O. The counter 1 is used as a timer. The data line of 8253 is directly connected to the BUS of 8031, and Ai and Ao are connected to the output of the address latch 74LS373 of 8031. The memory is allocated by line selection, that is, the 8253 chip select terminal CS (inverted) is connected to the P2.7 terminal of the 8031. It can be seen that the address of counter 0 is 7FFCH, the address of counter 1 is 7FFDH, the counter address is 7FFEH, and the mode control register port is 7FFFH.
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